RRAM structures have received increased attention because of their ability to combine fast operation at high densities for non-volatile data compared to other NVM devices. However, RRAM structures still suffer from several challenges, such as poor resistance uniformity, distribution of resistance states that may lead to smaller memory margins, and poor-performance back-end-of-the-line (BEOL) cell selectors.
A need therefore exists for methodology enabling RRAM structures with improved memory margins while maintaining simplicity and scalability, and the resulting structures.